This invention relates to comparator circuits. More particularly, it is concerned with comparator circuits employing offset correction circuitry.
Comparator circuits are well-known and widely used in various applications. A comparator circuit has two inputs and produces one output signal if the voltage at the first of the inputs is greater than that at the second, and produces another output signal if the voltage at the first input is less than that at the second. One application for comparator circuits is in analog-to-digital converters in which the voltages across a weighted network of capacitances are compared with a reference voltage to produce a set of digital output signals. One problem inherent with comparator circuits is a certain amount of offset. Although offset is due to internal imbalances, the effect is equivalent to the presence of a voltage, called the offset voltage, at one of the inputs. In effect the offset voltage is superimposed on the voltage applied to the one input, and the resulting voltage is compared with the voltage applied to the other input. The error due to the offset voltage may not be significant in some situations, but in certain applications such as in precise analog-to-digital converters the offset voltage may introduce significant error. Although various arrangements have been developed in order to cancel out or to compensate for the offset voltage in comparator circuits, it is desired to provide a simple arrangement which corrects for offset to within a predetermined residual error.